In the field of semiconductor technology there is an ever pressing need to increase the density of devices in integrated circuits. For example, a particular area in which increased device density is very important is that of memory devices. With memory devices, such as random access memory ("RAM"), dynamic random access memory ("DRAM"), read-only memory ("ROM"), programmable read-only memory ("PROM"), electrically erasable programmable read-only memory ("EEPROM"), and other types of memory, memory cells are arranged in arrays. By increasing the density of these memory cells, the array size, and therefore the amount of memory storage, is increased.
One limitation in increasing device density arises when contacts are needed from certain layers down to other layers. Because such contacts pass down through various layers, they must be carefully aligned to avoid interference with adjacent devices or conducting layers. These adjacent devices and conducting layers are formed to be spaced apart from the contact. However, if misalignment occurs when forming the contact, there can be short-circuiting and other device failures. To avoid these problems, existing designs allow sufficient room between various structures so that less than perfect alignment does not result in yield loss.
For example, in DRAM design, the spacing between certain contacts and adjacent structures is one of the most important parameters in determining the layout rules which will dictate the memory density of the DRAM. If a large space is chosen between a contact and an adjacent device in the design rules, the functional density of the chip goes down, and makes it less valuable. On the other hand, choosing a narrow space around contacts can cause device failure and yield loss, because of misalignment.